Maximum-Likelihood Stereo Correspondence using Field Programmable Gate Arrays

Abstract

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Typical software approaches tend to be too slow for real time performance on high frame rate (>= 30fps) stereo acquisition systems. Hardware implementations of these same algorithms allow for parallelization, providing a marked improvement in performance. This paper will explore one such hardware implementation of a maximum-likelihood stereo correspondence algorithm on a Field Programmable Gate Array (FPGA). The proposed ""FastTrack"" hardware implementation is a first stage prototype that demonstrates comparable results to an equivalent software implementation. with the advantage of high-speed (eventually up to 200fps) stereo depth estimation.